A Novel Framework for Functionally Untestable Transition Fault Avoidance during ATPG

Delay fault testing has proven to be a significant part of modern manufacturing testing. It has also become a source of overtesting due to detection of functionally untestable faults by invalid transitions that would not occur during functional operation of the chip. There has been previous work in the field that identifies these faults allowing them to be removed from active fault lists from ATPG tools. However, due to the random fill of don’tcare bits in test patterns, incidental detection of functionally untestable faults becomes possible. In this paper, we propose a novel framework that will generate patterns using any commercial ATPG that avoid detection of these functionally untestable transition faults. Previous methods have required modification of the ATPG tool itself or designing a new ATPG to avoid such faults, making the immediate use of these tools very difficult. Our framework builds upon a commercial ATPG tool and modifies the netlist rather than the tool. By using the present functionality of the ATPG tool and a modified netlist, pattern generation is structurally constrained to avoid generating a pattern that will incidentally detect a functionally untestable fault. The proposed minimally affects test coverage of functionally testable faults and does not significantly increase the amount of effort needed by the ATPG tool.